1. Field of Invention
The present invention relates to semiconductor memory devices such as SRAMs (static random access memories).
2. Description of Related Art
SRAMs, one type of semiconductor memory devices, do not require a refreshing operation, and therefore have characteristics that can simplify a system in which they are incorporated and facilitate lower power consumption. For this reason, the SRAMs are prevailingly used as memories for hand-carry type equipment, such as cellular phones.
It is preferable for the hand-carry type equipment to be reduced in size. Therefore, the memory size of the SRAMs must be reduced.
It is an object of the present invention to provide a semiconductor memory device that can reduce the size of memory cells.
In accordance with the present invention, a semiconductor memory device includes: a memory cell including a first driver transistor of a first conduction type, a second driver transistor of a first conduction type, a first load transistor of a second conduction type, a second load transistor of a second conduction type, a first transfer transistor of a first conduction type and a second transfer transistor of a first conduction type; a well contact region of a first conduction type; and a well contact region of a second conduction type. The memory cell, the well contact region of the first conduction type, and the well contact region of the second conduction type are provided in a plurality, respectively. The memory cell is equipped with first and second gate electrode layers, first and second drain-drain connection layers, and first and second drain-gate connection layers. The first gate electrode layer includes gate electrodes of the first driver transistor and the first load transistor. The second gate electrode layer includes gate electrodes of the second driver transistor and the second load transistor. The first drain-drain connection layer connects a drain region of the first driver transistor and a drain region of the first load transistor. The second drain-drain connection layer connects a drain region of the second driver transistor and a drain region of the second load transistor. The first drain-gate connection layer connects the first drain-drain connection layer and the second gate electrode layer. The second drain-gate connection layer connects the second drain-drain connection layer and the first gate electrode layer. The drain-gate connection layers, the drain-drain connection layers, and the gate electrode layers are provided in different layers, respectively, in plan view. The first and second gate electrode layers are located between the first drain-drain connection layer and the second drain-drain connection layer. The well contact region of the first conduction type is provided for each specified number of memory cells arranged in a first direction. The well contact region of the second conduction type is provided for every two of memory cells arranged in a second direction, which is perpendicular to the first direction.
The present invention is equipped with gate electrode layers that become gates of inverters, drain-drain connection layers that connect drains of the inverters, and drain-gate connection layers that connect gates of one of the inverters and drains of the other of the inverters. In accordance with the present invention, three layers (gate electrode layers, drain-drain connection layers, and drain-gate connection layers) are used to form flip-flops. Accordingly, patterns in each layer can be simplified (for example, into linear patterns) compared to the case in which flip-flops are formed using two layers. In this manner, in accordance with the present invention, since the patterns in each layer can be simplified, a miniaturized semiconductor memory device with its memory cell size being 4.5 xcexcm2 or smaller, for example, can be manufactured.
Also, in accordance with the present invention, in plan view, the first and second gate electrode layers are located between the first drain-drain connection layer and the second drain-drain connection layer. As a result, the source contact layer of the driver transistors can be disposed in the central area of the memory cell. Furthermore, wirings that connect the source contact layers to the grounding line can be disposed in the same layer as the drain-drain connection layers and in the center of the memory cell. Accordingly, the degree of freedom in forming the first and second drain-gate connection layers increases. This also facilitates reducing memory cell size. It is noted that, in the present invention, the source contact layer is a conduction layer that is used to connect a source region of the driver transistor to a wiring layer.
Also, in accordance with the present invention, latch-up is prevented. In other words, in a semiconductor memory device in accordance with the present invention, a well contact region can be disposed in a second conduction type well in which driver transistors and transfer transistors are formed for every two memory cells arranged in the second direction. Generally, when the transistors are operated and drain current flows, substrate current (current from an end of the drain to the well contact region) flows. In particular, the driver transistors have the largest substrate current. An increase in the potential that is the product of the substrate current and the substrate resistance (well resistance) causes latch-up. In the structure described above, a well contact region is formed in the memory cell, such that the driver transistor having a large substrate current is located close to the well contact region. As a result, the substrate resistance can be reduced, and therefore the generation of latch-up can be prevented.
Also, in accordance with the present invention, each one of the well contact regions of the second conduction type, which is disposed for every two of the memory cells arranged in the second direction, is disposed for every one of the memory cells arranged along the first direction. The first direction is the direction of the word lines. In general, when one of the word lines is selected, all of the memory cells connected to the word line are operated. In the driver transistors of the selected memory cells, drain current flows at once, and substrate current is generated at once. In accordance with the present invention, a well contact region per each cell is disposed for every one of the memory cells that are operated. As a result, the substrate resistance at all of the driver transistors in operation is lowered, and therefore the latch-up can be prevented. On the other hand, a well contact region is formed for each predetermined number of memory cells arranged in the first direction in the well of the first conduction type where the load transistors are formed. The predetermined number is, for example, 32 or 64. The load transistors only maintain a high potential at cell nodes, and direct current does not flow through the load transistors unlike the driver transistors, such that its substrate current is small. Therefore, for example, when the well contact region of the first conduction type is provided for every 32 cells, and the well resistance becomes large (in particular, a memory cell located intermediate of one well contact region and another well contact region has the largest well resistance), latch-up does not occur.
In accordance with the present invention, the first conduction type and the second conduction type may be set as follows. For example, the first conduction type is n-type and the second conduction type is p-type. Alternatively, the first conduction type is p-type, and the second conduction type is n-type. In a semiconductor memory device in accordance with the present invention, the first conduction type may preferably be n-type and the second conduction type may preferably be p-type. With this structure, an n-type well contact region is provided for each specified number of memory cells arranged in the first direction, and a p-type well contact region is provided for each two of the memory cells arranged in the second direction. P-channel transistors that become load transistors are formed in the n-type wells. N-channel transistors that become driver transistors or transfer transistors are formed in the p-type wells. In is noted that substrate current in an n-channel transistor is generally larger than that in a p-channel transistor. For example, when the substrate current per unit channel length of an n-channel transistor is 1 e-6 A/xcexcm, the substrate current per unit channel length of a p-channel transistor is 1 e-9 A/xcexcm, which makes a third-digit difference.
In the structure in accordance with the present invention, the region where the n-channel transistor, having a large substrate current is formed, is close to a well contact region, and therefore the substrate resistance is lowered. As a result, the generation of latch-up can be prevented. On the other hand, for the p-channel transistors, a well contact region is provided for, for example, every thirty-two memory cells, and the substrate resistance at the p-channel transistors becomes high. However, the substrate current is small, and therefore latch-up does not occur. It is noted that, in a semiconductor memory device in accordance with the present invention, the p-type well contact region is connected to the grounding line within the cell. Therefore, grounding wiring exclusively used for the p-type well contacts are not required, and therefore the semiconductor memory device can be miniaturized.
The present invention includes a plurality of word lines extending in the first direction. The word lines include gate electrodes of the first and second transfer transistors. Word line intermediate regions, where the first and second gate electrode layers are positioned, and word line intermediate regions, where the well contact regions of the second conduction type, are alternately arranged. This is one embodiment of the present invention in which a well contact region of the second conduction type is provided for every two of the memory cells arranged in the second direction.
In accordance with the present invention, word lines are in linear patterns. The patterns of the word lines are linear. As a result, the word lines can be made shorter compared to word lines having partially curved patterns. Therefore, the present invention can lower the resistance of the word lines. Also, when a word line is in a partially curved pattern, the curved portion may become narrower, which results in a localized increase in the gate wiring resistance caused by narrow line effect in a salicide process. In accordance with the present invention, the patterns of the word lines are linear, and do not have curved portions. As a result, the narrow line effect, which may be caused by the curved portions, does not occur, and an increase in the word line resistance that may be caused by the narrow line effect can be prevented.
Also, in accordance with the present invention, since the word lines are in linear patterns, the well contact region of the second conduction type can be positioned in an empty space in an intermediate region between word lines, without having to enlarge the memory cell area. Accordingly, in accordance with the present invention, a dead space (which is an extra space added for each specified number of memory cells to form a well contact region of the second conduction type and wiring to supply a well potential) is not required, and therefore the size of the semiconductor memory device can be reduced.
The present invention includes a plurality of source contact layers, wherein, in each of the memory cells, the first and second drain-gate connection layers are located in a layer above the first and second gate electrode layers, source regions of the first and second driver transistors are located in a gate electrode interlayer region that is a region between the first gate electrode layer and the second gate electrode layer, and each of the source contact layers is contained in an area above each of the gate electrode interlayer regions.
In accordance with the present invention, the drain-gate connection layers are located in a layer above the gate electrode layers and the drain-drain connection layers. As a result, the source contact layer can be contained in an area above each of the gate electrode interlayer regions while avoiding contact between the drain-gate connection layers and the source contact layers. Accordingly, in accordance with the present invention, the parasitic resistance of the source section of the driver transistor can be reduced. Also, since the source regions can be provided with simpler patterns (for example, a rectangular pattern having a generally uniform width), process margins, in particular, photo-process margins, in the manufacturing step for manufacturing semiconductor memory devices, can be expanded, such that the measurement precision in the channel width of driver transistors can be enhanced. Accordingly, in accordance with the present invention, the operation of memory cells can be stabilized.
Also, in accordance with the present invention, since the source contact layer can be contained in an area above each of the gate electrode interlayer regions, the word lines can be made in linear lines. As a result, an extra area in reserve can be provided in a boundary region between adjacent memory cells located next to one another in the second direction, namely, in a word line interlayer region. Accordingly, in accordance with the present invention, one well contact region of the second conduction type can be provided for every two of the memory cells arranged in the second direction without hindering the miniaturization of the memory cells. In this embodiment, one well contact region is disposed for every two of the memory cells in the second direction. However, in the first direction that may present more problems in actual operation, one well contact region is disposed for each one of the memory cells. Therefore, in accordance with the present invention, miniaturization of memory cells and semiconductor memory devices and prevention of latch-up can be simultaneously accomplished.
In accordance with the present invention, regions, where the first and second load transistors are to be formed, are positioned at both sides in the first direction of the well contact region of the first conduction type. In accordance with the present invention, the substrate resistance can be reduced. More specifically, the first and second load transistors are formed in the well of the first conduction type. The well of the first conduction type needs to be extended in order to connect the well contact region of the first conduction type to the well of the first conduction type. If the well contact region of the first conduction type is separated from the region where the first and second load transistors are formed, the length of the extended section of the well of the first conduction type becomes greater, which results in an increase in the substrate resistance. In accordance with the present invention, since the regions, where the first and second load transistors are to be formed, are positioned at both sides in the first direction of the well contact region of the first conduction type, the length of the extended section of the well of the first conduction type can be made smaller. As a result, in accordance with the present invention, the substrate resistance can be reduced.
In accordance with the present invention, the first conduction type is an n-type, the second conduction type is an n-type. The invention further includes first, second, third and fourth conduction layers. The first gate electrode layer, the second gate electrode layer and an auxiliary word line are located in the first conduction layer. The first drain-drain connection layer, the second drain-drain connection layer, a power supply line, a first contact pad layer, a second contact pad layer and a third contact pad layer are located in the second conduction layer. The first drain-gate connection layer, the second drain-gate connection layer, a main word line, a fourth contact pad layer, a fifth contact pad layer and a sixth contact pad layer are located in the third conduction layer. A first bit line, a second bit line and a grounding line are located in the fourth conduction layer. The auxiliary word line extends in a first direction. The power supply line connects to a source region of the first load transistor, a source region of the second load transistor and the well contact region of the first conduction type. The first contact pad layer is used to connect the first bit line and a source/drain region of the first transfer transistor. The second contact pad layer is used to connect the second bit line and a source/drain region of the second transfer transistor. The third contact pad layer is used to connect the well contact region of the second conduction type, a source region of the first driver transistor and a source region of the second driver transistor to the grounding line. The main word line extends in the first direction. The fourth contact pad layer is used to connect the first bit line and the source/drain region of the first transfer transistor. The fifth contact pad layer is used to connect the second bit line and the source/drain region of the second transfer transistor. The sixth contact pad layer is used to connect the well contact region of the second conduction type, the source region of the first driver transistor and the source region of the second driver transistor to the grounding line. The first and second bit lines extend in a second direction perpendicularly traversing the first direction.
In accordance with the present invention, a variety of characteristics required for semiconductor memory devices (for example, reduction in size, reliability, stability and speed) can be enhanced in a well-balanced manner. The xe2x80x9creduction in sizexe2x80x9d means both reduction of the size of each memory cell itself and the reduction of the size of the device that can be realized by the fact that grounding wires exclusively used for well contacts of the second conduction type are not required. The enhanced xe2x80x9creliabilityxe2x80x9d means improved reliability brought about by preventing latch-up. The enhanced xe2x80x9cstabilityxe2x80x9d means enhanced stability in the operation of memory cells, which is brought about by the reduced parasitic resistance in the driver transistors and the enhanced precision in the channel width. Also, the enhanced xe2x80x9cspeedxe2x80x9d means shortened access time, which is brought about by the reduced word line resistance.
In accordance with the present invention, the first gate electrode layer, the second gate electrode layer, the first drain-drain connection layer and the second drain-drain connection layer are in linear patterns, and are disposed in parallel with one another.